1. Field of the Invention
The present invention relates to an information processor. More particularly, the present invention relates to an information processor using ring data buses for the purpose of communication of data between a plurality of digital data processing units. Description of the Prior Art
Recently, attention has been paid to an architecture for a communication path between a plurality of digital data processing units. For example, a multiprocessor system is considered important because of its effectiveness in high speed digital data processing. In such a multiprocessor system, an architecture for a communication path between a plurality of processors becomes extremely significant. As a communication path between various kinds of digital data processing units such as a multiprocessor and peripheral devices, a ring data bus has been utilized.
FIG. 1 is a schematic block diagram showing an information processor using a conventional ring data bus, FIG. 2 is a block diagram showing in detail a input interface unit shown in FIG. 1, and FIG. 3 is a detailed block diagram of an output interface unit shown in FIG. 1.
Referring to FIGS. 1 to 3, an information processor using a conventional ring data bus will be described. Data processing units 1, 2 and 3 are connected to queue memories 10, 11 and 12 through data buses 20 through 22, input ready signal lines 23 through 25 and write signal lines 26 through 28. The queue memories 10, 11 and 12 are connected to input interface units 40, 41 and 42 through data buses 30 through 32, output ready signal lines 33 through 35 and shift signal lines 36 through 38. These input interfaces 40, 41 and 42 are connected in a ring fashion, together with output interfaces 70, 71 and 72. More particularly, the input interfaces 40, 41 and 42 and the output interfaces 70, 71 and 72 are connected, respectively, to data lines 50 through 55, acknowledge signal lines 56 through 61 and output ready signal lines 62 through 67, which are in the ring bus.
The output interfaces 70, 71 and 72 are connected to queue memories 13, 14 and 15 through data buses 80 through 82, input ready signal lines 83 through 85 and write signal lines 86 through 88. These queue memories 13, 14 and 15 are connected to data processing units 4, 5 and 6 through data buses 90 through 92, output ready signal lines 93 through 95 and read signal lines 96 through 98.
In FIG. 1, let us consider the situation where the output data from the particular data processing unit among three data processing unit 1, 2 and 3 should be transmitted to only a desired unit among three data processing units 4, 5 and 6. For example, in case where the data is transmitted from the data processing unit 2 to the data processing unit 4, the data processing unit 2 provides on the data bus 21 the data including data to be outputted and address information corresponding to the data processing unit 4 which is the destination. Then, the data processing unit 2 first confirms that the input ready signal line 24 of the queue memory 11 is a logical "1" and generates a write signal on the write signal line 27 so that the above described data can be stored in the queue memory 11 for the moment. Then, the queue memory 11 makes the output ready signal line 34 be a logical "1".
Incidentally, the logical "1" corresponds to a high level of a signal and the logical "0" corresponds to a low level of a signal.
If and when the input interface 41 verifies that the data field on the data line 51 is the empty slot and that the acknowledge signal line 58 of the ring bus is a logical "0", the above described data is read out of the queue memory 11 into the input interface 41 through the data bus 31 and is applied on the data line 52 of the ring bus. At that time, the input interface 41 simultaneously provides on the data line 52 of the ring bus a control bit indicating that the data on the data line 52 of the ring bus is the filled slot and generates a shift signal on the shift signal line 37 so that the output ready signal line 64 of the ring bus is rendered to be a logical "1".
The input interface 42 examines whether the data field on the data line 52 is an empty slot or not, after identifying that the output ready signal line 64 of the ring bus has changed to a logical "1". If and when the input interface 42 verifies that the data field on the data line 52 is not the empty slot, the interface 42 provides on the data line 53 the data, as it is, so that the acknowledge signal line 58 is rendered to be a logical "1" and the output ready signal line 65 is also rendered to be a logical "1".
After the input interface 72 verified that the output ready signal line 65 became a logical "1", the interface 72 verifies that the data field on the data line 53 is the empty slot and identifies the address information contained in the data. If and when the output interface 72 verifies that the address information does not correspond to the data processing unit 6, the interface 72 provides on the data line 54 the above described data, as it is, so that the acknowledge signal line 59 is rendered to be a logical "1" and the output ready signal line 66 is also rendered to be a logical "1".
An operation of the output interface 71 is the same as that of the above described output interface 72. That is, the data sent from the output interface 72 is applied to the data line 55 so that the acknowledge signal line 60 is rendered to be a logical "1" and the output ready signal line 67 is also rendered to be a logical "1".
When the input interface 70 verifies that the output ready signal line 67 has a logical "1", the interface 70 examines whether the data field applied to the data line 55 is the empty slot and identifies the address information contained in the data. If and when the output interface 70 verifies that the data field applied to the data line 55 is the empty slot and that the address information as identified corresponds to the data processing unit 4, the above described data is applied to the data bus 80 and the acknowledge signal line 61 is rendered to be a logical "1". When the input interface 70 verifies that the input ready signal line 83 is a logical "1", a write signal 86 is generated so that the above described data is written into the queue memory 13. Thereafter, the queue memory 13 renders the output ready signal line 93 to be a logical "1".
The data processing unit 4 generates a read signal on the read signal line 96 to read out the data from the queue memory 13 through the data bus 90, as long as the data processing unit 4 is in an enable state to receive data and the output ready signal 93 is a logical "1". Thus, a series of operations for data transmission is completed.
Now, referring to FIG. 2, the input interfaces 40 through 42 shown in FIG. 1 will be described in detail. The input interface 41 will be explained by way of an example. The input interface 41 comprises a control unit 100, a data switching portion 102, a latch 105, an empty slot verifier 106, and a control bit setter 110. The control unit 100 is responsive to a logical "1" in the output ready signal line 63 to verify that the input interface 40 applies the data to the data line 51. If and when the control unit 100 verifies that the output ready signal line 63 is a logical "1", a switching signal 101 is rendered to be a logical "0" so that the data is bypassed onto the data line 103 by the data switching portion 102.
The control unit 100 generates a latch signal 104 after the control unit 100 confirms that the acknowledge signal line 58 is a logical "0". If and when the control unit 100 generates a latch signal 104, the latch 105 latches the data. At the same time, the control unit 100 makes the acknowledge signal line 57 be a logical "1" and, after a delay time sufficient to fix the data latched in the latch 105 on the data line 52, the output ready signal line 64 is rendered to be a logical "1". The control unit 100 repeats a series of operations as described in the foregoing.
If and when the control unit 100 verifies that the output ready signal line 63 becomes a logical "0", the acknowledge signal line 57 is rendered to be a logical "0" and if and when the acknowledge signal line 58 becomes a logical "1", the output ready signal line 64 is rendered to be a logical "0". However, the control unit 100 operates in a discontinuous manner to perform the above described repeated operation at every pause cycle of the above operations, and performs the next interrupting operation, only in the event that the queue memory 11 outputs new data, that is, only if the queue memory 11 applies the data on the data bus 31 so that the output ready signal 34 is rendered to be a logical "1".
More particularly, after the output ready signal line 63 becomes a logical "1", the empty slot verifier 106 identifies a control bit 107 indicating that there is an empty slot on the data line 51 or not. If and when an empty slot verification result signal 108 is a logical "0", the control unit 100 makes a switching signal 101 a logical "0" in the same manner as the above described repeated operations, until the empty slot verification result signal 108 becomes a logical "1". The control unit 100 makes the data, as it is, on the data line 51 bypassed to the data line 103 and generates a latch signal 104 after confirming that the acknowledge signal line 58 is a logical "0". If and when the latch signal 104 is generated, the latch 105 latches the data. In addition, the control unit 100 makes the acknowledge signal line 57 a logical "1" and after a delay time period sufficient to fix the data latched in the latch 105 on the data line 52, the output ready signal line 64 is rendered to be a logical "1", which operation is repeated.
If and when the above described empty slot verification result signal 108 becomes a logical "1", the control unit 100 makes the switching signal 101 a logical "1" and the control bit setter 110 renders a control bit 109 a logical "0" which indicates that there is an empty slot on the data bus 31, and then the control bit 109 is added to the data. The data including the control bit 109 added thereto is bypassed to the data line 103. Then, the control unit 100 makes the acknowledge signal line 57 a logical "1" and generates a latch signal 104 after confirming that the acknowledge signal line 58 is a logical "0". The latch 105 latches the data in response to the latch signal 104.
The control unit 100 generates a shift signal 37 so that the new data appears on the data bus 31. In addition, after a sufficient delay time period to latch the data in the latch 105 on the data line 52 of the ring bus, the control unit 100 performs an operation for making the output ready signal line 64 a logical "1" and completes the above described interrupt operation. Incidentally, the other input interfaces 40 and 42 operate in the same manner.
Now, referring to FIG. 3, the output interfaces 70 through 72 will be described in detail. Taking the output interface 70 as an example, the output interface 70 comprises a control unit 111, an empty slot verifier 114, an address identifier 115, a data switching portion 119, a control bit setter 120 and a latch 125.
The control unit 111 is responsive to a logical "1" of the output ready signal line 67 to determine that the output interface 71 provides the data on the data line 55. The empty slot verifier 114 examines whether the data field applied to the data line 55 is the empty slot or not and the address identifier 115 identifies address information 113 contained in the data. The control unit 111 makes a switching signal 118 a logical "1", only when the data is a filled slot and address information 113 corresponds to the data processing unit 4, that is, only when the empty slot verification result signal 116 is a logical "0" and the address identifying result signal 117 is a logical "1".
If and when the switching signal 118 becomes a logical "1", the data applied on the data line 55 is bypassed to the data bus 80 as it is, by the data switching portion 119. A control unit 111 generates a write signal 86 to provide a queue memory 13 after the input ready signal line 83 from the queue memory 13 becomes a logical "1". In addition, the control unit 111 makes the acknowledge signal line 61 a logical "1" and provides an addition instruction signal 121 to a control bit setter 120. At that time, the data line 123 is in an open state, since the data switching portion 119 is switched to the queue memory 13.
Then, the control unit 111 verifies that the acknowledge signal line 56 is a logical "0" and renders to be a logical "1" a control bit 123 which indicates that the data field applied on the data line 122 is the empty slot. Then, the control unit 111 generates a latch signal 124 so that the control bit 123, which is rendered to be a logical "1", is latched in the latch 125. In addition, the control unit 111 makes the output ready signal line 62 a logical "1", after a sufficient delay time period to latch the data in the latch 125 on the data line 50 of the ring bus.
If and when the empty slot verification result signal 116 is a logical "1" or the address identification result signal 117 is a logical "0", the control unit 111 makes the switching signal 118 a logical "0" so that the data on the data line 55, as it is, is bypassed onto the data line 122. Then, the control unit 111 generates a latch signal 124 so that the data on the data line 122 is latched in the latch l25, after confirming that the acknowledge signal line 56 is a logical "0". In addition, the control unit 111 renders the acknowledge signal line 61 to be a logical "1" and, after a sufficient delay time period to fix the data latched in the latch 125 on the data line 50, the output ready signal line 62 is rendered to be a logical "1". The control unit 111 renders the acknowledge signal line to be a logical "0" at the time when the output ready signal line 67 of the ring bus becomes a logical "0". In addition, the control unit 111 renders the output ready signal line 62 to be a logical "0" at the time when the acknowledge signal line 56 becomes a logical "1". Other output interfaces 71 and 72 perform the same operation as that in the above described output interface 70.
As described in the foregoing the information processor as shown in FIG. 1 requires separate queue memories 10, 11, 12, 13, 14 and 15, respectively, for all of the input interfaces 40, 41, 42 and all of the output interfaces 70, 71, 72. For this reason, in the event that an amount of each data flowing into the ring buses sharply varies, that is, for example, in the event that a large amount of data is outputted only from the data processing unit 1 at a certain timing point and another large amount of data is outputted only from the data processing unit 3 at another timing point, the capacities of all of the queue memories 10 through 15 should be determined such that all of the queue memories 10 through 15 never cause overflow.
In other words, each of the queue memories 10 through 15 should have an extremely large memory capacity so that each of the queue memories 10 through 15 cannot overflow. For this reason, it is not suitable for making an information processor small-sized.
In addition, it is rare that all of the queue memories 10 through 15 are almost occupied and hence a use efficiency for using the queue memories 10 through 15 as a whole is extremely low
Furthermore, there is a disadvantage that a structure becomes complicated because control bits 107 and 112 indicating that the data field on the ring bus is the empty slot should be additionally required. More particularly, applying on the ring bus the data which is read out from the queue memories 10 through 15 to each of the input interfaces 40 through 42 requires a mechanism for resetting the above described control bit, that is, a control bit setter 110. In addition, a mechanism for monitoring said control bit on the data line of the ring bus on an input side, that is, an empty slot verifier 106 is required. Furthermore, a mechanism for monitoring said control bit on the data line on the input side, that is, the empty slot verifier 114 is also required in each of the output interfaces 70 through 72. Another mechanism for rendering to be logical "1" said control bit on the data line on the output side when the data on the ring bus on the input side is applied to the queue memories 10 through 15, the control bit setter 120 is also required. Further, as shown in FIGS. 2 and 3, the latches 105 and 125 are required in each interface. In these circumstances, the structure of each of the interfaces 40 through 42 and 70 through 72 becomes extremely complicated, which is a significant disadvantage.
On the other hand, with the recent advancement of semiconductor manufacturing techniques, many functional blocks are integrated in a semiconductor device with high density. In this case, because of a requirement for fast signal communication, functional coupling is made between functional blocks in a semiconductor integrated circuit device by using a metal wiring or metal silicide wiring or the like as data lines and control lines. However, with multiplication of function required for device, a proportion of occupation of said wiring regions in the device, particularly, address lines or data lines or control lines progressively increases. In addition, as described in the foregoing, in order to execute processing, such as fast data communication to an external device and fast operation in the device, without any stay of data, a large amount of registers or latches or first-in-first-out memories or the like for buffer storage of input-output communication data are required, in addition to the hardware necessary for realizing the information processing function.